Products

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Abaco FMC104 FPGA Mezzanine Card - Analog input

  • Four channel 14-bit 250 Msps A/D conversion
  • Available as air cooled and conduction cooled
  • VITA 57.1-2008 compliant
  • 1.5V to 3.3V VADJ operation
  • Based on TI ADS62P49
  • LVDS or 1.8V LVCMOS output operation
  • Coaxial front panel inputs on SSMC connectors
  • Single ended AC- or DC-coupled analog input
  • Optional analog differential input
  • Flexible clock tree enables:
    • internal clock
    • external clock
    • cascading multiple boards - Optional
  • LPC (low-pin count) compatible
  • Mil-I-46058c Conformal Coating Compliant - Optional

Abaco FMC108 FPGA Mezzanine Card - Analog input

  • Eight channel 14-bit 250Msps A/D conversion
  • Available as air cooled and conduction cooled
  • VITA 57.1-2008 compliant
  • 1.5V to 3.3V VADJ operation
  • Based on TI ADS62P49
  • LVDS or 1.8V LVCMOS output operation
  • Coaxial front panel inputs on SSMC connectors
  • Single ended AC- or DC-coupled analog input
  • Optional analog differential input
  • Flexible clock tree enables:
    • internal clock
    • external clock
    • cascading multiple boards – Optional
  • HPC (high-pin count) compatible
  • Mil-I-46058c Conformal Coating Compliant - Optional

Abaco FMC110 FPGA Mezzanine Card - Analog input and output

  • Dual - A/D - D/A Channel Operation
    • 2-channels 12-bit 1.0 Gsps A/D
    • 2-channels 16-bit 1.0 Gsps D/A
  • VITA 57.1-2010 compliant
  • Conduction Cooled - Standard Option
  • LVDS and 1.65V to 3.3V IO signalling
  • Single ended AC-coupled analog input
  • Clock Source, Sampling Frequency, and Calibration through an SPI communication bus
  • Flexible clock tree enables:
    • internal clock
    • external clock
    • internal clock with external reference
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • 6 Front panel SSMC connectors
  • 4 Rocket I/O pairs and 4 LVTTL lines available on the front pane

Abaco FMC112 FPGA Mezzanine Card - Analog input

  • 12 channel 14-bit 125 Msps A/D conversion
  • Conduction cooled compatible
  • ANSI/VITA 57.1-2010 compliant
  • Based on LTC2175-14
  • 1.5V to 3.3V VADJ operation
  • Single ended DC coupled inputs
  • Programmable DC offset correction
  • Flexible clock tree enables
    • External or Internal clock
    • External clock output
    • External or internal reference
  • LPC (low-pin count) compatible
  • Samtec QSE front panel connector mates with QTE series and EQCD and EQRF cable assemblies
  • Optional SSMC/MMCX clock and trigger IO on the back of the FMC (consult factory)
  • MIL-I-46058c compliant (optional)

Abaco FMC116 FPGA Mezzanine Card - Analog Input

  • 16 channel 14-bit 125 Msps A/D conversion
  • Conduction cooled compatible
  • ANSI/VITA 57.1-2010 compliant
  • Based on LTC2175-14
  • 1.5V to 3.3V VADJ operation
  • Single ended DC coupled inputs
  • Programmable DC offset correction
  • Flexible clock tree enables
    • External or Internal clock
    • External clock output
    • External or internal reference
  • HPC (high-pin count) compatible
  • Samtec QSE front panel connector mates with QTE series and EQCD and EQRF cable assemblies
  • Optional SSMC/MMCX clock and trigger IO on the back of the FMC (consult factory)
  • MIL-I-46058c conformal coating (optional)

Abaco FMC120 FPGA Mezzanine Card - Quad channel 16-bit A/D @ 1 Gsps quad channel 16-bit D/A @ 1.25 Gsps Simultaneous Sampling @ 1 Gsps

  • 4-Channels 16-bit 1.00 Gsps A/D
    • 1.5 GHz Analog Bandwidth
    • Usable in the 3rd Nyquist Zone
  • 4-Channels 16-bit up to 1.25 Gsps D/A
    • 2.8 GSPS Update Rate
    • Onboard 48-Bit NCO for Flexible Signal Placement
  • VITA 57.1 HPC compliant
  • Conduction Cooled – Standard Option
  • DC coupled analog input.
  • Internal clock or external clock
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC – High Pin Count Connector
  • 10 front panel SSMC or MMCX connectors
  • 2Kbit EEPROM (M24C02- WDW) accessible from the Host via I2C bus

Abaco FMC121 FPGA Mezzanine Card - Analog input and output

  • 2-Channels 16-bit 1.0 Gsps A/D
    • 1.5 GHz Analog Bandwidth
    • Usable in the 3rd Nyquist Zone
  • 2-Channels 16-bit 1.4 Gsps D/A
    • 2.8 GSPS Update Rate
    • Onboard 48-Bit NCO for Flexible Signal Placement
  • VITA 57.1 HPC compliant
  • Conduction Cooled - Standard Option
  • DC coupled analog input and output.
  • Internal clock or external clock
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC - High Pin Count Connector
  • 6 front panel SSMC or MMCX connectors
  • 2Kbit EEPROM (M24C02- WDW) accessible from the Host via I2C bus

Abaco FMC122 FPGA Mezzanine Card - Multi-mode analog input

  • Dual - Single 8-Bit Channel Operation
    • 2-Channel 1.25 Gsps A/D conversion Mode
    • 1-Channel 2.50 Gsps A/D conversion Mode
  • VITA 57.1-2010 compliant
  • 1.5V to 3.3V VADJ operation
  • Conduction Cooled
  • 1.25Gsps or 625Msps DDR LVDS outputs
  • Coax front panel inputs on SSMC connectors
  • Single ended AC-coupled analog inputs
  • Flexible clock tree enables: - internal clock - external clock - cascading multiple boards (optional)
    • LPC (low-pin count) compatible
    • Mil-I-46058c Conformal Coating Compliant (optional) X

Abaco FMC123 FPGA Mezzanine Card - Analog input

  • 4-Channels 16-bit 1.00 Gsps A/D
    • 1.5 GHz Analog Bandwidth
    • Usable in the 3rd Nyquist Zone
  • VITA 57.1 compliant
  • Conduction Cooled - Standard Option
  • DC coupled analog input
  • Internal clock or external clock
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC - High Pin Count Connector
  • 6 front panel SSMC or MMCX connectors
  • 2Kbit EEPROM (M24C02- WDW) accessible from the Host via I2C bus

Abaco FMC125 FPGA Mezzanine Card - Multi-mode analog input

  • • Quad - Dual - Single 8-Bit Channel Operation
    • 4-Channel 1.25 Gsps A/D conversion Mode
    • 2-Channel 2.50 Gsps A/D conversion Mode
    • 1-Channel 5.00 Gsps A/D conversion Mode
  • VITA 57.1-2010 compliant
  • 1.5V to 3.3V VADJ operation
  • Conduction Cooled
  • 1.25Gsps or 625Msps DDR LVDS outputs
  • Coax front panel inputs on SSMC connectors
  • Single ended AC-coupled analog inputs
  • Flexible clock tree enables:
    • internal clock
    • external clock
    • cascading multiple boards (optional)
  • HPC (high-pin count) compatible
  • Mil-I-46058c Conformal Coating Compliant (optional)

Abaco FMC126 FPGA Mezzanine Card - Multi-mode analog input

  • Quad - Dual - Single 10-Bit Channel Operation
    • 4-Channel 1.25 Gsps A/D conversion Mode
    • 2-Channel 2.50 Gsps A/D conversion Mode
    • 1-Channel 5.00 Gsps A/D conversion Mode
  • VITA 57.1-2010 compliant
  • 1.5V to 3.3V VADJ operation
  • Conduction Cooled
  • 1.25Gsps DDR LVDS outputs
  • Coax front panel inputs on SSMC connectors
  • Single ended AC-coupled analog inputs
  • Flexible clock tree enables
    • internal clock
    • external clock
    • cascading multiple boards (optional)
  • HPC (high-pin count) compatible
  • Mil-I-46058c Conformal Coating Compliant (optional)

Abaco FMC134 FPGA Mezzanine Card - Direct RF conversion module

  • Two operational modes
    • 4 channels, 12-bit, 3.2GSPS data rate
    • 2 channels, 12-bit, 6.4GSPS data rate
  • VITA 57.4 HSPC FMC+ site required
  • 16 JESD204B lanes at 12.8GBPS
  • 8 JESD204B lanes passed to board topside for FMC stacking
  • Optional FMC+e connection for additional stacked serial lanes
  • Conduction cooled configuration available
  • AC-coupled analog input
  • 9 front panel SSMC or MMCX connectors
  • Internal or external clock
  • MIL-I-46058c conformal coating (optional)
  • 2Kbit EEPROM (M24C02-WDW) accessible from the host via I2C bus
  • Full-featured board support package.
    • Open source VHDL reference design
    • Open source C/C++ reference examples. Windows® and Linux® support.
    • JESD204B core included
    • Simplified IP integration with StellarIP

Abaco FMC140 FPGA Mezzanine Card - Analog input

  • Four-channel, 16-bit A/D up to 370 MSPS
  • VITA 57.1-2010 compliant
  • JESD204B serial interface
  • Conduction-cooled – Standard Option
  • AC or DC-coupled analog signals
  • 6 SSMC/MMCX front panel connectors
  • Clock source, sampling frequency, and calibration through SPI communication busses
  • Flexible clock tree enables:
    • Internal clock source
    • External sampling or reference clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC (high-pin count) compatible

Abaco FMC142 FPGA Mezzanine Card - Analog input and output

  • Two-channel, 16-bit A/D up to 370 MSPS
  • Two-channel, 16-bit D/A up to 2.5 GSPS
  • VITA 57.1-2010 compliant
  • JESD204B serial interface
  • Conduction-cooled – Standard Option
  • AC or DC-coupled analog signals
  • 6 SSMC/MMCX front panel connectors
  • Clock source, sampling frequency, and calibration through SPI communication busses
  • Flexible clock tree enables:
    • Internal clock source
    • External sampling or reference clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC (high-pin count) compatible

Abaco FMC151 FPGA Mezzanine Card - Analog input and output

  • Quad Channel Operation
    • 2-channels 14-bit A/D up to 250 Msps
    • 2-channels 16-bit D/A up to 800 Msps
  • VITA 57.1-2010 compliant
  • Conduction Cooled - Standard Option
  • Single ended DC-coupled analog signals
  • Digitally controlled offset correction
  • 6 MMCX/SSMC connectors available from the front panel
  • Clock Source, Sampling Frequency,and Calibration settings through SPI communication busses
  • Flexible clock tree enables:
    • internal clock source (VCXO)
    • external sampling or reference clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • LPC (low-pin count) compatible
  • LVDS and 1.65V to 3.3V IO signalling X

Abaco FMC160 FPGA Mezzanine Card - Analog input and output

  • One ADC12D1800: Single channel 12-bit 3.6Gsps
  • One AD9129: Single channel 14-bit D/A up to 5.7 Gsps (2.85Gsps without 1:2 interpolation) - LVDS
  • VITA 57.1-2010 compliant
  • Conduction Cooled - Standard Option
  • Single ended AC-coupled analog signals
  • 6 MMCX/SSMC connectors available from the front panel
  • 4 LVTTL signals available from an HDMI connector on the front panel
  • 4 Xilinx MGT available from an HDMI connector on the front panel
  • Clock Source, Sampling Frequency through SPI communication busses
  • Flexible clock tree enables:
    • on board VCO: 2200MHz - 4400MHz
    • external reference clock
    • external sampling clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC (high-pin count) compatible
  • LVDS IO signaling X

Abaco FMC161 FPGA Mezzanine Card - Multi-mode analog input

  • One ADC12D1800: Single channel 12-bit 3.6Gsps or dual channel at 1.8Gsps
  • VITA 57.1-2010 compliant
  • Conduction Cooled – Standard Option
  • Single ended AC-coupled analog signals
  • 5 MMCX/SSMC connectors available from the front panel
  • 4 LVTTL signals available from an HDMI connector on the front panel
  • 4 Xilinx MGT available from an HDMI connector on the front panel
  • Clock Source, Sampling Frequency through SPI communication busses
  • Flexible clock tree enables:
    • on board VCO: 2200MHz - 4400MHz
    • external reference clock
    • external sampling clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC (high-pin count) compatible
  • LVDS IO signaling X

Abaco FMC163 FPGA Mezzanine Card - Multi-mode analog input, single mode analog output

  • One ADC12D2000RF: Singlechannel 12-bit 4Gsps or dualchannel 12-bit 2Gsps
  • One AD9129: Single-channel 14-bit D/A up to 5.7 Gsps (2.85Gsps without 1:2 interpolation) - LVDS
  • VITA 57.1-2010 compliant
  • Single-ended, AC-coupled analog signals
  • 6 MMCX/SSMC connectors available from the front panel
  • 4 LVTTL signals available from an HDMI connector on the front panel
  • 4 Xilinx MGT available from an HDMI connector on the front panel
  • Clock source, sampling frequency through SPI communication busses
  • Flexible clock tree enables:
    • Onboard VCO: 2200MHz - 4400MHz
    • External reference clock
    • External sampling clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC (high-pin count) compatible
  • LVDS IO signaling

Abaco FMC164 FPGA Mezzanine Card - Analog input

  • Four channel 16-bit 250MSPS A/D conversion
  • Available as air cooled and conduction cooled
  • VITA 57.1-2010 compliant
  • Based on TI ADS42LB69
  • Coaxial front panel inputs on SSMC connectors
  • Single ended AC- or DC-coupled analog input
  • Differential analog inputs - Optional
  • Flexible clock tree enables:
    • internal clock
    • internal clock locked to an external reference
    • external clock
    • external sync / 1PPS
  • LPC (low-pin count) compatible
  • Mil-I-46058c Conformal Coating Compliant – Optional

Abaco FMC168 FPGA Mezzanine Card - Analog input

  • Eight channel 16-bit 250MSPS A/D conversion
  • Available as air cooled and conduction cooled
  • VITA 57.1-2010 compliant
  • Based on TI ADS42LB69
  • Coaxial front panel inputs on SSMC connectors
  • Single ended AC- or DC-coupled analog input
  • Flexible clock tree enables:
    • internal clock
    • internal clock locked to an external reference
    • external clock
    • external sync / 1PPS
  • LPC (low-pin count) compatible
  • Mil-I-46058c Conformal Coating Compliant - Optional

Abaco FMC170 FPGA Mezzanine Card - High speed analog input and output

  • Single-channel, 10-bit A/D up to 5Gsps
  • Single-channel, 10-bit D/A up to 5Gsps
  • VITA 57.1-2010 compliant
  • Conduction-cooled – Standard Option
  • AC-coupled analog signals
  • LVDS IO signaling
  • 6 SSMC or MMCX front panel connectors
  • Clock source, sampling frequency, and calibration through I2C communication
  • Flexible clock tree enables:
    • Internal clock source
    • External sampling or reference clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC (high-pin count) compatible

Abaco FMC176 FPGA Mezzanine Card - Analog input and output

  • Two AD9250: 4-channel 14-bit A/D up to 250 Msps - JESD204B
  • Two AD9129: 2-channel 14-bit D/A up to 5.6 Gsps (2.8Gsps without 2:1 interpolation) - LVDS
  • VITA 57.1-2010 compliant
  • Conduction Cooled - Standard Option
  • Single ended AC-coupled analog signals
  • 10 MMCX/SSMC connectors available from the front panel
  • Clock Source, Sampling Frequency, and Calibration through a SPI communication busses
  • Flexible clock tree enables:
    • on board VCO: 2300MHz - 2650MHz
    • external reference clock
    • external sampling clock
  • Power-down modes to switch off unused functions for system power savings
  • Mil-I-46058c Conformal Coating Compliant (optional)
  • HPC (high-pin count) compatible
  • LVDS IO signaling

Abaco FMC204 FPGA Mezzanine Card - Analog output

  • Quad channel 16-bit 1 Gsps D/A conversion
  • VITA 57.1-2010 compliant
  • Conduction Cooled - Standard Option
  • LVDS and 1.65V to 3.3V IO signalling
  • Single ended AC-coupled analog output
  • Clock Source, Sampling Frequency, and Calibration settings through an SPI communication bus
  • Flexible clock tree enables
    • internal sampling clock
    • external reference and sampling clock
  • HPC (high-pin count) compatible
  • 6 Front panel SSMC connectors
  • 4 Rocket I/O pairs and 4 LVTTL lines available on the front panel
  • Power-down modes to switch off unused functions for system power savings
  • HDMI connector for user defined signaling
  • Mil-I-46058c Conformal Coating Compliant (Optional)

Abaco FMC216 FPGA Mezzanine Card - Analog output

  • 16 channel 16-bit 312.5Msps D/A conversion
  • Conduction cooled compatible
  • ANSI/VITA 57.1-2010 compliant
  • Based on DAC39J84
  • 1.65V to 3.3V VADJ operation
  • Single ended DC coupled outputs
  • Programmable DC offset correction
  • Flexible clock tree enables
    • External or Internal clock
    • External clock output
    • External or internal reference
  • HPC (High-Pin Count) 400 pins connector
  • Samtec QSE front panel connector mates with QTE series and EQCD and EQRF cable assemblies with SMA connectors
  • MIL-I-46058c conformal coating (optional)

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