XJFlash Example Timings 

Minimum theoretical time for conventional boundary scan: 35 minutes. 

Total XJFlash run time: 10.5 s to 32.6 s.

XJFlash will automatically step through four stages each time a flash device is programmed: 

• Initialisation – The FPGA connected to the flash is configured with the XJFlash image required for the target board. Example time: 2.1 s. 
• Erase – The flash can be erased using one of two algorithms. The basic erase will simply erase all blocks within a defined range (this may be the whole flash or just the space needed for the image to be programmed). The more intelligent erase will use the fact that it is quicker to read the flash than to erase it; as such it reads from each address and only starts erasing if some data is found. This step can be skipped if it is known that the flash will always be blank before it is programmed. Example time – intelligent erase enabled: 0.9 s with a device already erased, to 23 s with a fully programmed device (limited by erase time of device). 
• Program – Data from the target images is streamed into the FPGA through its JTAG port. The FPGA then programs this data into the connected flash(s). Multiple files can be specified and programmed at defined offsets. This step can be bypassed if only verification is required. Example time: 6.2 s (limited by the programming speed of the device). 
• Verify – The verification checks every byte in the flash against the specified file(s), ensuring there are no data bit errors. This step can be bypassed if only programming or erasing is required. Example time: 1.8 s with TCK at 10 MHz, reducing to 1.3 s with TCK at 20 MHz. 

These example times are provided for a Spartan-6 XC6SLX9 programming a 2 MByte pseudorandom data file into the FPGA’s SPI configuration PROM.

Example Timings Using a Xilinx Zynq®-7000 series SoC 

A 256 Mbit file can be programmed into a SPI NOR flash and verified in around 46 s, depending on the TCK speed and the memory type being used*; 32 Mbit of code takes just over 7 s.

Adding an initial erase cycle adds only 3.1 s for an empty 256 Mbit flash, or 54 s for a full one. That drops to 0.4 s and between 6.5 and 9.2 s respectively for a 32 Mbit device. 

^{* TCK = 66 MHz, pseudorandom data file. Time varies with flash type.}

Example Timings Using a Xilinx Zynq® UltraScale+™ series SoC 

A 256 Mbit file can be programmed into a SPI NOR flash and verified in around 42 s, depending on the TCK speed and the memory type being used**; 32 Mbit of code takes 7 s.

Adding an initial erase cycle adds only 2 s for an empty 256 Mbit flash, or 57 s for a full one. That drops to 0.3 s and 6.9 s respectively for a 32 Mbit device. 

^{** TCK = 30 MHz, pseudorandom data file. Time varies with flash type.}

Design requirements - Can I  use XJFlash?

In order to use XJFlash all of the data, address and control signals on the flash device(s) must be connected to an FPGA on the target board. This can be a configuration PROM, or a flash device connected to any general purpose I/O pin. These connections can be direct, indirect, dedicated or shared: Direct connections – YES

Direct connections – YES

The flash is directly connected to the FPGA. 

Indirect connections – YES

1. The flash is connected to the FPGA via a buffer 
2. Some of the address signals are shared with the data signals and connected via a latch. 
3. There is another configurable device, such as a CPLD between the flash and the FPGA. 

Shared connections – YES

The flash is connected to the FPGA in one of the modes described above but these connections are shared with another device (such as a processor). 

No connections – YES (with design changes)

If your design contains an FPGA but the flash is not connected in any of the configurations described, it may be possible to use spare pins on the FPGA to establish connections to the flash. These connections would not be used in the mission mode of the board but would allow you to use XJFlash to perform fast flash programming. If your FPGA is already connected to the same address/data bus as the flash then this may not require many extra signals. 

No FPGA – Not directly

Unfortunately, it is not possible to use XJFlash if there is no FPGA. However, if it is possible to bring the connections of the flash to a header or test points on the board, XJFlash fast programming can be used via those connections using an XJAccelerator card. 

Alternatively, it may be possible to do fast flash programming using the debug interface on a processor – please contact us to see if you can use this approach on your board.

Supported FPGAs

 Compatibility 

• Intel (Altera) – Arria GX, Arria II GX, Arria II GZ, Arria V, Arria V GZ, Arria 10, Cyclone, Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV E, Cyclone IV GX, Cyclone V, Stratix, Stratix GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Stratix V, Stratix 10 
• Lattice – MachXO2, LatticeECP3, LatticeXP2 
• Microsemi – IGLOO2, ProASIC3, ProASIC3E, ProASIC3L, SmartFusion2 
• Xilinx – Artix-7, Kintex-7, Kintex UltraScale, Kintex UltraScale+, Spartan-3, Spartan-3A, Spartan-3E, Spartan-6, Spartan-7, Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5, Virtex-6, Virtex-7, Virtex UltraScale, Virtex UltraScale+, Zynq-7000, Zynq UltraScale+ 

This list is continuously growing, so contact us for the latest details. 

^{All trademarks are the property of their respective owners.} 

Recommended system requirements 

• Intel® Core i3, i5, i7 processor or equivalent (any generation) 
• Microsoft® Windows® 8, Windows 8.1, Windows 10 (1607 and later), or Windows 11 (32 or 64 bit) 
• 4 GB of RAM