Reduce corporate-wide software overhead and time to production Standardize on ONE common, open-platform interface for all internal RF/Microwave or power projects Modular design allows for scalable solutions in increments of 72 high-current sink, 12 reset/control and 32 TTL I/O channels

Combine up to 12 fail-safe building blocks, dual SPDT, SP4T, SP6T, or transfer switch in a compact 1U footprint Front “pluggable” relays facilitate field maintenance Embedded web interface provides interactive utility to monitor and control relays from anywhere in the world

True wire-speed impairment @ 100Gbps (plus 50 / 40 /25 & 10Gbps) Ease of use – Chimera is a stand-alone impairment tool that integrates seamlessly with Xena’s Valkyrie traffic generator, letting you speed up your work flow by using the same SW to both generate and impair Ethernet traffic.

Automated firewall performance characterization Automated traffic profile generation from traffic monitoring logs Application emulation for NGFW performance, SSL decryption, and NAT Unencrypted and encrypted malware test

Easy-to-use UI (“2-clicks” to get a stream running) Wide range of optical & copper test modules for testing all speeds up to 800GE Thor-400G-7S-1P & Thor-100G5S-1P are the only test modules on the market that can test AN/ LT as well as PAM4-based speeds (50, 100, 200 and 400GE) and NRZ based speeds (10, 25, 40, 50 and 100GE)

World’s fastest production line tester Ultra-simple web-browser UI - 3 clicks to complete test cycle Seamless parallel test case execution Displays test status, progress, and real time logs

Responsive and easy to use management software Highly scalable UDP/TCP layer 4 traffic generation High performance TLS testing suite

Xena OpenAutomation (XOA) is an open-source test automation framework for use with Xena’s Valkyrie & Vulcan Traffic Generation & Analysis (TGA) solutions and Chimera, our network impairment emulator. Fast, easy to use and extremely flexible, XOA features a Python API that runs on any OS.

Fast flash programming  Increases UUT test coverage with additional interface connectivity  Easy integration with XJTAG test systems

Only BSDL files required to get the board up and running  Set up pin states – e.g. low, high, toggling  Trace shorts, opens and other signals  Easy low-level access to device pins/busses  Clear display of the pins/balls with variable zoom levels and split screen  View JTAG chain data as waveforms  Quickly find and monitor changing pins  Program devices with SVF and STAPL files  Real-time interaction  XJIntegration (use XJAnalyser functionality from other software)

Reduce your time spent debugging boards due to high precision fault isolation  Improve your time to market and reduce project risk by early design verification  Reduce your test development time by reusing tests from prototype/design in manufacturing and field support  Ongoing time savings by test reuse across projects

Reduce flash programming times  SPI, QSPI, parallel NOR flash devices supported  Support for NAND flash devices available on request  Shortened development cycles  No need for additional equipment  Can be used for fast firmware upgrade  No FPGA development required