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Description:

Traditional PDN measurement methods focus on component or board-level measurements. However, it is crucial to measure and validate the PDN impedance profile from the die to the VRM while the chip is powered.

This paper presents a straightforward method to measure the in-situ system-level PDN impedance profile from the die’s perspective, including from the on-die capacitance to the VRM, suitable for sub-milliohm impedances and GHz frequencies in powered or unpowered states. The method employs the 2-port shunt VNA technique with independent package-lead connections to the chip.

Three key features enable this method: UFL connectors on the board for VCC pin connections, a novel de-embedding method to reduce pigtail impact, and a DC blocking capacitor for powered chip measurements. Implemented with any 2-port VNA and analyzed with tools like QUCS, this technique was validated using a Rohde and Schwarz ZNL VNA.

Applied to a microcontroller-based system with both optimized and pathological PDNs, this method accurately characterizes key PDN elements and highlights the importance of in situ on-die measurements compared to on-board measurements.

Type: Technical Paper Session

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